1. Field of the Invention
The present invention relates to a conductive layer connecting structure and a method of manufacturing the same, and in particular to a conductive layer connecting structure used in a semiconductor device as well as a method of manufacturing the same.
2. Description of the Background Art
Demands for semiconductor memory devices have been rapidly increased owing to rapid and wide spread of information equipments such as computers. Regarding a function, devices having a large-scale storage capacity and a high operation speed have been demanded. In view of this, technical development has been made for improving a density, a responsibility and a reliability of semiconductor memory devices.
DRAMs (Dynamic Random Access Memories) are well known as a kind of semiconductor memory devices allowing random input/output of storage information. For improving a density of the DRAM, a memory cell size must be reduced. As the memory cell size is reduced, a planar area occupied by a capacitor is also reduced. This results in reduction in quantity of charges which can be stored in the capacity (i.e., quantity of charges which can be stored in the memory cell of 1 bit). If the quantity of charges storable in the memory cell of 1 bit is lower than a predetermined value, the DRAM functioning as a storage region performs an instable operation, and the reliability lowers.
In order to prevent an instable operation of the DRAM, it is necessary to increase a capacity of the capacitor while keeping an occupied planar area within a predetermined range. As measures for increasing a capacity of the capacitor, measures such as (1) reduction in thickness of a capacitor dielectric film, and (2) increase in a dielectric constant of the capacitor dielectric film have been studied.
Reduction in thickness of the capacitor dielectric film at the above item (1) has already been achieved to a maximum extent in a usual structure using a silicon oxide film as the capacitor dielectric film. Therefore, the capacitor must have a complicated form such as a cylindrical form or a fin-like form so as to increase the capacitor capacity using the silicon oxide film as the capacitor dielectric film. However, an extremely complicated process is required for manufacturing the capacitor having the above complicated form.
Accordingly, development for increasing the capacitor dielectric constant in the above item (2) has recently been made. In order to increase the dielectric constant of the capacitor dielectric film, the capacitor dielectric film may be made of a material having a high dielectric constant which is called a high dielectric constant material. This high dielectric constant material generally has a dielectric constant which is several to hundreds of times larger than that of a silicon oxide film. By using the high dielectric constant material as the capacitor dielectric film, the capacity can be increased without complicating a form of the capacitor.
Materials called high dielectric constant materials are, for example, tantalum pentoxide (Ta.sub.2 O.sub.5), lead zirconate titanate (PZT), lead lanthanum zirconate titanate (PLZT), strontium titanate (STO) and barium titanate (BTO) and barium strontium titanate (BST).
Since these high dielectric constant materials are crystallizable, platinum group elements having lattice constants close to that of high dielectric constant material is used at a portion which is in contact with the high dielectric constant material. Therefore, the capacitor of the conventional DRAM has a conductive layer connecting structure in which platinum group elements are electrically connected to a silicon substrate.
However, the platinum group elements have high reactivity with elements such as silicon. In a structure where the platinum group elements and the silicon are in contact with each other, thermal processing at a temperature of 400.degree. C. easily causes a solid phase reaction, by which, for example, platinum silicide is formed between platinum and silicon. This changes a crystal structure of platinum, and prevents epitaxial growth of the high dielectric constant material at the surface of platinum. When the high dielectric constant material is to be formed, an oxidizing atmosphere is required, in which platinum silicide is oxidized to form a silicon oxide film at the surface of platinum silicide. This silicon oxide film has a lower dielectric constant than the high dielectric constant material, so that it reduces the dielectric constant of the dielectric film.
In order to use a high dielectric constant material as a dielectric film of a capacitor, therefore, a layer for preventing diffusion is required between a lower electrode layer made of platinum and a conductive layer made of polycrystalline silicon as well as between an upper electrode layer made of platinum and an interconnection layer on the capacitor. Generally, diffusion preventing layers are formed of titanium nitride which is widely used as barrier metal for aluminum interconnection layers. It is known that such diffusion preventing layers can property function at up to about 500.degree. C.
The following references have disclose DRAMs having capacitors which use the high dielectric constant material as capacitor dielectric films.
(1) Japanese Patent Laying-Open No. 7-38068 (1995).
(2) International Electron Devices Meeting (IEDM) 92, pp. 267-270.
A DRAM disclosed in the above reference (1) will be described below with reference to the drawings.
FIG. 33 is a cross section showing a conductive layer connecting structure in a DRAM disclosed in Japanese Patent Laying-Open No. 7-38068. Referring to FIG. 33, isolation oxide film 1033s are formed at a surface of a silicon substrate 1031. Channel stopper regions 1035 are in contact with the lower surfaces of isolation oxide films 1033, respectively. A plurality of transfer gate transistors 1030 are formed at the surface of silicon substrate 1031 electrically isolated by isolation oxide films 1033 and channel stopper regions 1035.
Each transfer gate transistor 1030 has a gate oxide film 1021, a gate electrode 1023 and impurity regions 1025. Gate electrode 1023 is formed on a region between impurity regions 1025 with gate oxide film 1021 therebetween. A silicon oxide film 1027 covers the surface of gate electrode 1023.
There is formed a bit line 1037, which extends over the surface of silicon oxide film 1027 and is in contact with one of impurity regions 1025. Bit line 1037 and transfer gate transistor 1030 are covered with silicon oxide film 1001 and silicon nitride film 1003.
Silicon nitride film 1003 is layered over silicon oxide film 1001. Since bit line 1037 is covered with silicon oxide film 1001 and silicon nitride film 1003, it forms a buried bit line.
Silicon oxide film 1001 and silicon nitride film 1003 are provided with contact holes 1001a and 1003a reaching the surfaces of impurity regions 1025. Contact holes 1001a and 1003a are filled with plug layers 1009a which are in contact with impurity regions 1025.
Capacitors 1020 are electrically connected to impurity regions 1025 via plug layers 1009a, respectively.
Each capacitor 1020 has a lower electrode layer 1013a, a capacitor dielectric film 1015 and an upper electrode layer 1017. The lower electrode layer 1013a is formed over the surface of silicon nitride film 1003 with a barrier layer 1011a therebetween, and has a film thickness from 30 to 100 nm. Lower electrode layer 1013a is made of platinum (Pt).
Barrier layer 1011a has a three-layer structure made of titanium (Ti), titanium nitride (TiN) and titanium (Ti), and is in contact with plug layer 1009a. Each of films forming barrier layer 1011a has a thickness from 10 to 50 nm. Barrier layer 1011a prevents diffusion of impurity from plug layer 1009a made of doped polycrystalline silicon into lower electrode 1013a, and also serves to improve adhesion between silicon nitride film 1003 and lower electrode layer 1013a.
A capacitor dielectric film 1015 is formed over the surface of lower electrode layer 1013a. Capacitor dielectric film 1015 is made of a high dielectric constant material such as BST. An upper electrode layer 1017 is formed over lower electrode layer 1013a with capacitor dielectric film 1015 therebetween. Upper electrode layer 1017 is made of, e.g., platinum. Alternatively, it may be made of doped polycrystalline silicon. Capacitor 1020 is covered with a silicon oxide film 1019.
Description will be given on a method of manufacturing the conductive layer connecting structure in the DRAM shown in FIG. 33.
FIGS. 34 to 45 are cross sections showing steps of manufacturing the conductive layer connecting structure in the conventional DRAM shown in FIG. 33.
Referring to FIG. 34, transfer gate transistors 1030 having gate oxide films 1021, gate electrodes 1023 and impurity regions 1025 are formed at the region in silicon substrate 1031 isolated by isolation oxide films 1033. A step is also performed to form bit line 1037 which extends over the surface of silicon oxide film 1027 covering the surface of gate electrode 1023 and is in contact with one of impurity regions 1025.
A low pressure CVD method is performed to form silicon oxide film 1001 covering bit lines 1037 and transfer gate transistors 1030 over the entire surface of silicon substrate 1031.
Referring to FIG. 35, a CVD method is also performed to form silicon nitride film (Si.sub.3 N.sub.4) 1003 over the surface of silicon oxide film 1001. A step is performed to from silicon oxide film 1005 over the entire surface of silicon nitride film 1003 by a CVD method.
Referring to FIG. 36, photoresist 1041 is applied to the entire surface of silicon oxide film 1005. Exposure or the like is performed to pattern photoresist 1041 for forming hole patterns 1041a located above impurity regions 1025. Anisotropic etching is effected on silicon oxide film 1005 masked by photoresist 1041. This etching forms openings 1005a at silicon oxide film 1005. Then, photoresist 1041 is removed.
Referring to FIG. 37, a CVD method is performed to form second silicon oxide film 1007 covering the inner walls of openings 1005a and the entire surface of silicon oxide film 1005. Second silicon oxide film 1007 is etched back to expose at least the surface of silicon nitride film 1003 at the bottom of each opening 1005a.
Referring to FIG. 38, the above etch back forms a rim or collar 1007a having a configuration of a side wall spacer at the side wall of opening 1005a.
Referring to FIG. 39, anisotropic etching is effected on silicon nitride film 1003 masked by rims 1007a and first silicon oxide film 1005. Thereby, contact holes 1003a exposing portions of the surface of silicon oxide film 1001 are formed.
Referring to FIG. 40, anisotropic etching is effected on silicon oxide film 1001 masked by silicon nitride film 1003. This anisotropic etching effected on silicon oxide film 1001 also removes silicon oxide film 1005 and rims 1007a. Also, this etching forms contact holes 1001a at silicon oxide film 1001.
Referring to FIG. 41, a CVD method is performed to form doped polycrystalline silicon film 1009, which has a thickness from 500 to 600 nm and fills contact holes 1001a and 1003a, over the entire surface of silicon nitride film 1003.
Referring to FIG. 42, etch back is performed on doped polycrystalline silicon film 1009 and silicon nitride film 1003 to an extent indicated by dotted line in FIG. 41. Thereby, plug layers 1009a are formed.
Referring to FIG. 43, a sputtering method is performed to form successively three layers, i.e., titanium layer, titanium nitride layer and titanium later forming barrier layer 1011 and each having a thickness from 10 to 50 nm over the whole surface defined by plug layers 1009a and silicon nitride film 1003. A sputtering method is performed to form platinum layer 1013 from 30 to 100 nm in thickness over the entire surface of barrier layer 1011.
Referring to FIG. 44, photoresist 1043 patterned into an intended configuration is formed over the surface of platinum layer 1013. Platinum layer 1013 and barrier layer 1011 masked by photoresist 1043 are anisotropically etched and patterned. This patterning forms lower electrode layer 1013 made of platinum and electrically connected to impurity regions 1025 via plug layers 1009a.
Referring to FIG. 45, a sputtering method is performed to form capacitor dielectric film 1015 made of a high dielectric constant material such as BST and covering the surface of lower electrode layer 1013a.
Referring to FIG. 33, a step is performed to form an upper electrode layer 1017 made of a platinum layer and covering lower electrode layer 1013 with capacitor dielectric film 1015 therebetween. Lower electrode layer 1013, capacitor dielectric film 1015 and upper electrode layer 1017 form capacitor 1020. Silicon oxide film 1019 is formed over capacitor 1020.
Description will now be given on problems which arise from the conductive layer connecting structure in the conventional DRAM described above.
FIG. 46 is a cross section for illustrating a problem arising from the conductive layer connecting structure in the conventional DRAM. Referring to FIG. 46, a memory cell region 2000 provided with memory cells is higher in level than a peripheral circuit region 3000. In the structure where silicon oxide film 1019 covers memory cell region 2000 and peripheral circuit region 3000, silicon oxide film 1019 has a difference in level at and near the boundary between memory cell region 2000 and peripheral circuit region 3000.
This difference in level may cause a problem in a photolithographic process, and thus is not preferable. In order to reduce the level difference, therefore, an interlayer reflow is generally performed to heat and thereby flatten silicon oxide film 1019. The interlayer reflow reduces the level difference by moving the surface of silicon oxide film 1019 to a position indicated by dotted line 1019a.
The interlayer reflow requires heating of silicon oxide film 1019 to a temperature from 700 to 800.degree. C. When heated to such a high temperature, the titanium nitride layer contained in barrier layer 1011 does not generally function as a diffusion barrier. Therefore, heating to a high temperature causes mutual diffusion between silicon in plug layer 1009b and platinum in lower electrode layer 1013a, whereby the platinum and silicon react with each other to deposit platinum silicide at the surface of lower electrode layer 1013a. Silicon in the platinum silicide is oxidized to form a silicon oxide film. This silicon oxide film has a dielectric constant significantly lower than that of a high dielectric constant material such as PZT, so that the silicon oxide film thus produced significantly reduces a capacity of the capacitor.